1. Field of the Invention
The present invention relates to arrangement of bus lines transmitting a signal used to determine a word line address of a plurality of memory cell arrays of a semiconductor memory device, and in particular to an output line (bus) arrangement structure of a row decoding array.
2. Description of the Background Art
An output signal of a row decoding array is a word line enable signal Pxi and a word line disable signal /Pxi. In general, a high voltage and an inside voltage are employed as an operational voltage, respectively at enable and disable states. A functional block of receiving the two signals, and connecting them to a final word line is a sub-word line driver (SWD).
As illustrated in FIG. 1, a conventional output line (bus) arrangement structure of the row decoding array is controlled according to the word line enable signal Pxi and the word line disable signal /Pxi applied from a word line driver 17 to an output line 15 of the row decoding array in order to drive a cell block 11 including: a unit memory array 12 consisting of a plurality of sub-memory cell arrays 10 and a plurality of sub-word line drivers 13; and a main row decoder 14 connected to one end portion of the unit memory array 12, and selects a final word line CWL&lt;0&gt; by the sub-word line driver 13.
Here, each unit memory array 12 employs one output line 15 of the row decoding array. At the same time, a unit bit sense amp 16 consisting of a plurality of bit sense amps is positioned below the output line 15 of the row decoding array. In addition, when a row address of 2 bits is used for decoding the word line driver 17, as shown in FIG. 1, four unit memory arrays 12, four word line drivers 17 and four output lines of the row decoding array are used.
However, in the conventional output line arrangement structure for the row decoding array, one word line driver 17 must control the four unit memory arrays 12, and thus a delay corresponding to four times of a unit memory array word line transmission speed is generated. As a result, a high speed operation is difficult to perform. In addition, the output line 15 of the row decoder array is arranged at every unit bit sense amp 16, and thus an area for line arrangement is increased by four times.